Simulate CPU Architecture

Design a minimal but complete CPU by defining an instruction set architecture, composing an ALU and register file into a datapath, designing a control unit that generates the correct signals for each instruction phase, implementing the fetch-decode-execute cycle, simulating a small program to completion, and verifying every clock cycle against expected register and memory state.

When to Use

• Learning or teaching computer architecture from first principles
• Designing a custom processor for an FPGA or educational simulator
• Verifying understanding of how instructions execute at the gate and register-transfer level
• Building a software simulation (Python, JavaScript, or structured walkthrough) of a CPU
• Composing the combinational blocks from design-logic-circuit and the sequential blocks from build-sequential-circuit into a working system

Inputs

• Required: Processor complexity target -- 4-bit, 8-bit, or 16-bit data width; number of general-purpose registers (2-16)
• Required: Minimum instruction set -- at least: load, store, add, subtract, bitwise AND/OR, branch, halt
• Optional: Addressing modes beyond direct (immediate, register-indirect, indexed)
• Optional: Additional instructions (multiply, shift, compare, jump-and-link for subroutines)
• Optional: Memory size and word size