tpu-pipeline-scheduler
TPU Pipeline Scheduler
Analyze register-level pipeline scheduling for TPU v7x kernels. Given an explicit sequence of instructions with VPR assignments, this skill detects data hazards, schedules across hardware units, analyzes VPR pressure, and suggests optimal ordering.
When to Use
- Designing optimal instruction interleaving for a Pallas kernel tile
- Analyzing VPR register pressure to determine if a tiling strategy is feasible
- Identifying data dependency bottlenecks (RAW/WAR/WAW hazards)
- Comparing alternative instruction orderings for pipeline efficiency
Input Format: Pipeline IR
The input is a JSON file describing a sequence of hardware instructions with explicit VPR assignments:
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