tpu-pipeline-scheduler

Installation
SKILL.md

TPU Pipeline Scheduler

Analyze register-level pipeline scheduling for TPU v7x kernels. Given an explicit sequence of instructions with VPR assignments, this skill detects data hazards, schedules across hardware units, analyzes VPR pressure, and suggests optimal ordering.

When to Use

  • Designing optimal instruction interleaving for a Pallas kernel tile
  • Analyzing VPR register pressure to determine if a tiling strategy is feasible
  • Identifying data dependency bottlenecks (RAW/WAR/WAW hazards)
  • Comparing alternative instruction orderings for pipeline efficiency

Input Format: Pipeline IR

The input is a JSON file describing a sequence of hardware instructions with explicit VPR assignments:

Related skills
Installs
1
First Seen
7 days ago