verilog-sv-language
Verilog/SystemVerilog Language Skill
Expert skill for Verilog and SystemVerilog development following IEEE 1364 and IEEE 1800 standards. Provides deep expertise in synthesizable RTL code generation, proper construct usage, and modern coding practices.
Overview
The Verilog/SystemVerilog Language skill enables comprehensive HDL development for FPGA and ASIC designs, supporting:
- IEEE 1800-2017 SystemVerilog standard
- Verilog-2005 backward compatibility
- Proper always_ff, always_comb, always_latch usage
- SystemVerilog interfaces and modports
- Parameterized modules with localparam
- Packed and unpacked arrays
- Packages and imports
Capabilities
1. Proper Always Block Usage
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