MLX model porting and optimization

Mission

Produce or inspect a correct, reproducible, architecture-aware MLX implementation. Correctness comes before speed. Every speed or memory claim must name the hardware, software versions, workload, baseline, and quality gate.

Dense decoders have an executable capture/scaffold/schema-2 conversion/parity chain proven by one Qwen2.5 port. The other 16 families have tooled routing/planning/generic validation but runbook-guided module implementation. Exact output is the only built-in task metric; domain evaluators remain future work.

When to use this skill

• Use for porting, converting, running, inspecting, quantizing, packaging, or publishing a PyTorch/Hugging Face model or existing project on MLX/Apple Silicon.
• Use for parity, NaN/Inf, shape, tokenizer, preprocessing, output, performance, memory, cache, serving, benchmark, or provenance problems in an MLX port.
• Do not use for CUDA/non-Apple targets, general ML theory without an MLX target, or unrelated training from scratch.