SystemVerilog Development
Installation
SKILL.md
SystemVerilog Development
Provide expert guidance for SystemVerilog RTL design following IEEE 1800-2017 standards.
Always Block Conventions
Use modern SystemVerilog constructs:
| Purpose | Construct | Pattern |
|---|---|---|
| Flip-flops | always_ff |
always_ff @(posedge clk or negedge rst_n) |
| Combinational | always_comb |
always_comb begin ... end |
| Latches (rare) | always_latch |
always_latch begin ... end |