SystemVerilog Lint Fix Patterns

Error-specific fix patterns for common SystemVerilog lint issues.

WIDTHTRUNC / WIDTHEXPAND

Message: Width mismatch in assignment

Diagnosis: Signal widths don't match between source and destination.

Fixes:

// Truncation (wide to narrow) - explicit slice
logic [15:0] wide;
logic [7:0]  narrow;
assign narrow = wide[7:0];

// Extension (narrow to wide) - zero extend
assign wide = {8'b0, narrow};