The Agent Skills Directory

[SAFE]: The skill provides static templates for SystemVerilog testbenches including clock generation, reset sequences, and assertions. All code snippets use standard hardware description language (HDL) syntax.
[SAFE]: File operations are limited to standard simulation tasks such as $dumpfile and $dumpvars, which are used to generate waveform data within the simulation environment and do not pose a risk to the host system.
[SAFE]: No network operations, credential exposures, or shell command executions were identified. The instructions are purely technical and specific to the stated purpose of hardware design verification.

SystemVerilog Testbench Patterns