GF Errors — Hardware Error Translation

When any tool produces an error, translate it through three layers before presenting to the user. NEVER show raw tool output without translation.

Translation Protocol

For every error from Verilator, Yosys, GHDL, or simulation:

Layer 1 — WHAT (one sentence, plain English)

State what happened. No technical jargon. No tool names.

• BAD: "%Error: counter.sv:15:17: Cannot find signal: 'clk_in'"
• GOOD: "The signal clk_in doesn't exist in this module."

Layer 2 — WHY (1-2 sentences, context)

Explain why it happened. Reference specific lines and names.

• "Your module declares its clock input as clk (line 5), but the always block on line 15 references clk_in. These names must match."