HLS FPGA

objective

Translate algorithmic kernels into efficient FPGA implementations using high-level synthesis and systematic pragma optimization.

workflow

1. define kernel interfaces, throughput target, and initiation interval goals.
2. apply hls pragmas for pipelining, unrolling, and memory partitioning.
3. synthesize and compare latency-resource tradeoffs across pragma sets.
4. validate c-simulation, co-simulation, and post-synthesis equivalence.
5. promote hls design only after stable qos and verification coverage.

required diagnostics

• initiation interval and loop-latency target attainment.
• pragma sensitivity on area-throughput frontier.
• c-model versus rtl co-simulation mismatch rate.
• memory bandwidth bottleneck diagnostics.
• build-to-build reproducibility of synthesis outcomes.