FPGA Development

Treat HDL as a description of concurrent hardware with explicit temporal and electrical interfaces. A correct design requires consistent functional intent, language semantics, clock/reset behavior, implementation constraints and verification evidence. Compilation, simulation, synthesis, timing and physical observation establish different facts.

Operating contract

1. Identify the requested decision and design boundary: new RTL, review, simulation failure, resource problem, CDC/timing analysis, implementation or hardware release. Use the smallest complete evidence set for that decision.
2. Record device/package, board revision, clocks, reset, I/O voltage and pin constraints before making target-specific claims. Pure RTL reasoning can proceed from a stated abstract interface without inventing a board.
3. State transaction semantics, latency, throughput, backpressure, loss/duplication policy, initialization and arithmetic behavior before implementation. A waveform picture is not an interface contract.
4. Keep synthesizable design and verification-only constructs separate. Match the HDL subset and vendor primitive model to the actual simulator and synthesizer versions.
5. Review constraint coverage and exception intent before interpreting slack. A green summary with missing clocks or unconstrained endpoints is incomplete evidence.
6. Before programming, resetting, erasing or otherwise changing connected hardware, confirm the target, scope, and rollback path before acting. Read-only discovery may proceed without confirmation. Bitstreams and programming paths must match the exact target.
7. Retain artifacts tied to one source/constraint/tool/device configuration. Do not combine yesterday's tests with today's unverified bitstream into a release claim.

Task routing

Read only the relevant depth references; use their templates to retain reviewable decisions.