dsphdl DDC: Design, Simulate, Generate HDL

Overview

End-to-end MATLAB workflow for designing a Digital Down Converter (DDC) using dsphdl System objects — combining an NCO (local oscillator), complex mixer, and multi-stage decimation filter chain — then simulating the streaming HDL-optimized design and generating synthesizable HDL via HDL Coder.

Integer decimation (all stages have integer rate change):

RF Input → [Mixer] → [CIC Decimator] → [Compensation FIR Decimator] → Baseband Output
              ↑
           [NCO] (generates cos + jsin at carrier frequency)

Non-integer decimation (uses Farrow for fine rate adjustment):

RF Input → [Mixer] → [CIC Dec (xR)] → [Farrow (L/M)] → [FIR Dec (xD)] → Baseband Output
              ↑
           [NCO]