Detecting Design Errors (SLDV DED + Root Cause Analysis)

When to Use

• User asks to check a Simulink model for design errors (division-by-zero, overflow, dead logic, out-of-bounds)
• User asks to find root causes of DED findings
• User asks to fix or understand an analysis finding
• User asks why there is missing coverage due to dead logic (dead logic gates prevent coverage objectives from being satisfied)
• User has SLDV artifacts (.mat file) and wants analysis without re-running DED

When NOT to Use

• Requirement verification — checking if a model satisfies a requirement
• Test generation or test authoring — creating test cases from requirements or for coverage
• Comprehensive verification — this skill is a quick defect scan, not an exhaustive proof; a clean result does not guarantee the model is free of all errors
• Coverage measurement — this skill does not measure or report model coverage; use Simulink Coverage tools

Safety Rules