CPU Pipelines and Hazards

Purpose

Explain classic and modern CPU pipeline concepts: stages, data and control hazards, forwarding/bypassing, stalls, and branch handling — foundational for optimization and understanding microarchitecture counters.

When to Use

• Interpreting pipeline stall metrics from skills/profilers/intel-vtune-amd-uprof
• Teaching why instruction order affects throughput
• Relating assembly scheduling to hardware behavior
• Debugging unexpected performance cliffs in hot loops

Workflow

1. Five-stage classic pipeline (MIPS-style mental model)