Memory Hierarchy and Caches

Purpose

Teach CPU memory hierarchy: cache levels, associativity, line size, coherence protocols, false sharing, and prefetch behavior — architectural depth complementing optimization practice in skills/low-level-programming/cpu-cache-opt.

When to Use

• Explaining why padding fixes scalability
• Choosing struct layout for multicore
• Interpreting cache miss counters
• Understanding DMA vs CPU cache on embedded SoCs

Workflow

1. Hierarchy (typical desktop/ server)