RISC-V Privileged Architecture

Purpose

Guide agents through the RISC-V privileged specification: M/S/U privilege modes, CSR registers, trap handling, PLIC and CLINT interrupt controllers, OpenSBI firmware integration, Sv39/Sv48 page tables, and QEMU virt machine testing.

When to Use

• Writing an OS kernel or hypervisor for RISC-V
• Implementing trap handlers and context switch
• Integrating OpenSBI for S-mode firmware services
• Configuring interrupt controllers on QEMU virt or hardware
• Setting up virtual memory with Sv39 or Sv48
• Porting xv6-RISC-V or bare-metal firmware

Workflow

1. Privilege levels