HSB IP Create Top Skill

Purpose

Create a fixed-format SystemVerilog top-level scaffold that instantiates HOLOLINK_top and declares the HSB-facing signals required by a validated HOLOLINK_def.svh.

This skill owns only the top-level scaffold around the HSB IP:

• SPDX/Apache license header
• HOLOLINK_def.svh include
• FPGA_top module shell
• HSB-facing signal declarations
• HOLOLINK_top instantiation
• comments/TODOs for top-level integration

Use hsb-ip-def for HOLOLINK_def.svh generation and validation. Do not create or validate the defs file here.

Prerequisites