cuTile Python DSL — Language-Specific Guidance

Prerequisite: Load /design-kernel for shared naming, versioning, KernelPlan structure, composition patterns, clone workflow, devlog template, and designer output contract. This skill covers only cuTile-specific runtime patterns and constraints.

When To Use cuTile Python DSL

Stay in cuTile Python DSL (cutile-dsl) when the next optimization is still expressible through:

• tile sizes and tensor layout choices,
• CTA remapping and work partitioning via ct.bid() / ct.num_blocks(),
• occupancy and cluster-size hints (num_ctas, occupancy),
• compiler guidance such as latency / allow_tma hints,
• multi-stage composition through KernelPipeline / ConcurrentKernels.

Suitability Gate

Do not expect cuTile to express explicit intra-CTA scheduling. The public execution model does not expose thread, warp, or warpgroup identity, and does not allow explicit synchronization or communication within a block. Likewise, num_ctas does not give you a public cluster programming model: there is no exposed cluster rank, cluster barrier, DSM primitive, or cluster memory scope.

This becomes a hard design constraint when profiling shows the kernel is pinned to one CTA per SM. In that regime, the usual recovery path in state-of-the-art kernels is explicit scheduling inside the CTA: warpgroup seesaw schedules, producer/consumer pipelines, barrier choreography, or cluster-cooperative overlap. If the optimization you need falls in that category, stop iterating inside cuTile and switch to CuTe DSL (/design-cute-dsl-kernel).