SoC Pipeline

Coordinate work; do not implement RTL or testbench content in the coordinator.

Preflight

1. Read ../../rules/01_swarm_flow.md, ../../rules/02_toolchain.md, ../../rules/05_pipeline_state.md, and ../../rules/13_review_gate.md when review or commit readiness is in scope. Read coding style or exceptions only when relevant. For any architecture, documentation, RTL, verification, synthesis, physical-design, or material refactoring task, also read ../../rules/06_design_knowledge.md and query soc-ai-kb before design decisions.
2. Resolve the absolute module workspace and module name.
3. Query pipeline_state.json; initialize it only when absent. Never overwrite existing state implicitly.
4. For chip-level, subsystem-level, or multi-module requirements without an approved architecture handoff, dispatch soc-architect first for IP selection, technology/process selection, and the overall SoC integration architecture plan. Treat it as pre-doc planning, not a pipeline_state.json stage.
5. Select the RTL role:
   • normal logic: soc-rtl-designer
   • top integration: soc-integrator
   • CRG: soc-crg-engineer, only when crg-gen is registered
   • OpenROAD physical-design handoff: soc-pd-engineer
6. Select soc-reviewer for post-stage, pre-commit, or validation-evidence audit. The reviewer reports findings only and never closes a pipeline stage. Use .agents/scripts/check_loop_state.py <workspace> --mode normal after stage work and --mode strict before commit readiness when a workspace is available.
7. Reviewer dispatch includes relevant review domains, reports and delivery inputs, knowledge-base scope, and the structured output contract from 13_review_gate.md. Missing knowledge-base rules require Need Human Confirmation; they are never synthesized from memory.

Delegation