Assertion-Based Specification Design

SVA methodology treating assertions as executable specifications, not testbench utilities.

Core Principle (MANDATORY)

Specifications SHALL be written as SystemVerilog Assertions

• Natural language explanations are secondary and optional
• RTL implementation details MUST NOT be referenced unless unavoidable
• Written assertions MUST be sufficient to understand intended behavior without reading RTL
• Assertions define what the design must do, not how it does it

When to Use This Skill