Plan Feature Lowering (SV -> HIR -> MIR)

Guide for implementing a SystemVerilog feature end-to-end, starting from LRM semantics and ending with passing JIT backend tests.

Prerequisites

Read before starting:

• docs/pipeline-contract.md - what each layer is responsible for
• docs/mir-design.md - MIR semantics + purity/effects model
• docs/hir-design.md - HIR node taxonomy + typing rules
• docs/error-handling.md - error types, when to use each
• docs/type-system.md - type interning, type kinds, 4-state representation

Mental Model

The LRM defines semantics. HIR makes semantics explicit and typed. MIR is the semantic endpoint -- the lowest IR before code generation. The LLVM backend is a translation target, not a semantic decision-maker.