formal-verification
Installation
SKILL.md
Formal Verification Skill
Overview
Expert skill for formal property verification and model checking, enabling exhaustive verification of FPGA design properties without simulation.
Capabilities
- Write properties for formal verification
- Configure formal tool constraints
- Analyze formal counterexamples
- Apply bounded model checking
- Configure cover and assume directives
- Debug formal failures
- Integrate formal with simulation flows
- Support JasperGold and VC Formal flows