UVM Verification Methodology

UVM testbench design patterns and best practices for the AXIUART_RV32I verification environment.

When to Use This Skill

• Creating UVM testbench components (tests, environments, agents)
• Implementing drivers, monitors, sequences, or scoreboards
• Debugging UVM configuration or communication issues
• Resolving UVM naming convention questions
• Setting up factory patterns or objection management

UVM Component Naming

Component Hierarchy