SystemVerilog Verification
Installation
SKILL.md
SystemVerilog Verification Reference
SVA (SystemVerilog Assertions)
Assertion Types
| Type | Use Case | Example |
|---|---|---|
| Immediate | Procedural checks | assert (a == b) else $error("mismatch"); |
| Concurrent | Temporal sequences | `assert property (@(posedge clk) req |
Temporal Operators
// Sequence operators
##N // Delay N cycles
##[M:N] // Delay M to N cycles
##[0:$] // Eventually (use sparingly - unbounded)