SystemVerilog Verification
Pass
Audited by Gen Agent Trust Hub on Apr 26, 2026
Risk Level: SAFE
Full Analysis
- [SAFE]: The skill is a purely informational reference for hardware engineering tasks. It provides templates for SystemVerilog Assertions (SVA), functional coverage, and testbench architecture.
- [SAFE]: All code snippets use standard SystemVerilog syntax for hardware simulation (e.g.,
$display,$dumpfile,$randomize). These are executed within specialized hardware simulators and do not interact with the host operating system's shell or network. - [SAFE]: No external dependencies, remote script downloads, or obfuscated content were detected.
- [SAFE]: No prompt injection or data exfiltration patterns are present.
Audit Metadata