chip-design-engineer
Pass
Audited by Gen Agent Trust Hub on Apr 22, 2026
Risk Level: SAFE
Full Analysis
- [SAFE]: The skill is a comprehensive knowledge base and persona definition for ASIC design engineering. It contains instructional content, code snippets for Verilog and TCL, and industry-standard workflows.
- [SAFE]: No network operations (curl, wget, etc.) or file system modifications were detected. The skill does not attempt to access sensitive user data or environment variables.
- [SAFE]: There are no signs of prompt injection or attempts to bypass AI safety guidelines. The instructions are focused on providing expert-level technical advice in the semiconductor domain.
- [SAFE]: The skill mentions various industry-standard tools (Synopsys, Cadence, Mentor) but does not provide scripts that execute these tools or download them from external sources. The Python references are for industry-standard testbench methodologies (cocotb) and are purely informational.
Audit Metadata